FPGA

Published in UC Berkeley, EECS, 2019

Overview

I learnt RTL design through the HDL language Verilog. I implemented basic circuits, I generated verilog code in python to synthesis the RAM containing an audio signal in .wav to be played on the audio output of the FPGA controlling a PWM signal.

I also used VCS and SystemVerilog to simulate circuits and check waveforms

Course website